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Configurable Multiplier Modules for an Adaptive Computing System : Volume 4, Issue 9 (06/09/2006)

By Pfänder, O. A.

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Book Id: WPLBN0003985272
Format Type: PDF Article :
File Size: Pages 6
Reproduction Date: 2015

Title: Configurable Multiplier Modules for an Adaptive Computing System : Volume 4, Issue 9 (06/09/2006)  
Author: Pfänder, O. A.
Volume: Vol. 4, Issue 9
Language: English
Subject: Science, Advances, Radio
Collections: Periodicals: Journal and Magazine Collection (Contemporary), Copernicus GmbH
Historic
Publication Date:
2006
Publisher: Copernicus Gmbh, Göttingen, Germany
Member Page: Copernicus Publications

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Pfleiderer, H., Lachowicz, S. W., & Pfänder, O. A. (2006). Configurable Multiplier Modules for an Adaptive Computing System : Volume 4, Issue 9 (06/09/2006). Retrieved from http://www.worldlibrary.org/


Description
Description: Microelectronics Department, University of Ulm, Germany. The importance of reconfigurable hardware is increasing steadily. For example, the primary approach of using adaptive systems based on programmable gate arrays and configurable routing resources has gone mainstream and high-performance programmable logic devices are rivaling traditional application-specific hardwired integrated circuits. Also, the idea of moving from the 2-D domain into a 3-D design which stacks several active layers above each other is gaining momentum in research and industry, to cope with the demand for smaller devices with a higher scale of integration. However, optimized arithmetic blocks in course-grain reconfigurable arrays as well as field-programmable architectures still play an important role. In countless digital systems and signal processing applications, the multiplication is one of the critical challenges, where in many cases a trade-off between area usage and data throughput has to be made. But the a priori choice of word-length and number representation can also be replaced by a dynamic choice at run-time, in order to improve flexibility, area efficiency and the level of parallelism in computation. In this contribution, we look at an adaptive computing system called 3-D-SoftChip to point out what parameters are crucial to implement flexible multiplier blocks into optimized elements for accelerated processing. The 3-D-SoftChip architecture uses a novel approach to 3-dimensional integration based on flip-chip bonding with indium bumps. The modular construction, the introduction of interfaces to realize the exchange of intermediate data, and the reconfigurable sign handling approach will be explained, as well as a beneficial way to handle and distribute the numerous required control signals.

Summary
Configurable multiplier modules for an adaptive computing system

Excerpt
Joyner, J W., Zarkesh-Ha, P J., and Meindl, J D.: Global Interconnect Design in a Three-Dimensional System-on-chip, IEEE Transactions on VLSI systems, 2004.; Baugh, C R. and Wooley, B A.: A Two's Complement Parallel Array Multiplication Algorithm, IEEE Trans. Computers, C-22, 1045–1047, 1973.; Bermak, A., Martinez, D., and Noullet, J.-L.: High-Density 16/8/4-bit Configurable Multiplier, IEE Proc. Circuits Devices Systems, 144, 272–276, 1997.; Davis, W R., Wilson, J., Mick, S., Xu, J., Hua, H., Mineo, C., Sule, A M., Steer, M., and Franzon, P D.: Demystifying 3D ICs: The Pros and Cons of Going Vertical, IEEE Design & Test of Computers, 22, 498–509, 2005.; Eshraghian, S., Lachowicz, S., and Eshraghian, K.: Ultra High Bandwidth Image and Data Processing using 3-D Vertically Integrated Architectures, Proceedings of the SCI 2003, Orlando, FL, X, 189–195, 2003.; Hwang, K.: Computer Arithmetic – Principles, Architecture, and Design, John Wiley and Sons, New York, 1979.; Haynes, S D., Ferrari, A B., and Cheung, P. Y K.: Flexible Reconfigurable Multiplier Blocks suitable for enhancing the Architecture of FPGAs, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, San Diego, CA, 191–194, 1999.; Pfänder, O A. and Pfleiderer, H.-J.: Dynamische Rekonfiguration von arithmetischen Einheiten auf Bitebene, Advances in Radio Science 2004, Miltenberg, Germany, 319–323, 2004.; Pfänder, O A., Lachowicz, S W., and Pfleiderer, H.-J.: Flexible Multiplier Blocks for Accelerated Processing in a 3D-SoftChip Adaptive Computing System, Proceedings of the IFIP VLSI-SoC 2005, Perth, Western Australia, 485–491, 2005.; Xilinx: Virtex\texttrademark-II Platform FPGAs and Product Specification, Xilinx Document DS031 (v3.4), 2005.

 

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